Can I force or probe a signal in vhdl module from verilog top testbench?I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?
Some of the more recent versions of IUS (ncsim) will take '.' as the hierarchical separator through a mixed language hierarchy. In older versions, you would have to guess at when to use '.' and ':' through a hierarchical reference.If you're not sure, bring up the design browser and scope down into the module you are interested in and the design browser will show you the hierarchical path with the appropriate delimiters.Let us know if this doesn't answer your question.Harlin!
The testbench is verilog and the design is VHDL. So we instantiate the VHDL design (em0) at the verilog top level and force signals as follows:signal -force em0__ec0__fp0__flport_1__secnt_mclr 0(this is for the Palladium)hope that helps!
Hey, Tom!Also, in Palladium, once it goes through design import, there's no language difference (in reality, after HDLICE it's generally all verilog netlists). You can set the delimiterRule to verilog and then use '.' as hierarchical delimiter for the entire design. Using '.' is even more advantageous when you start with a gate-level netlist that usually contains instance names like '\a.b.c.d_456' or the like. Those things get ugly real fast.Harlin!
hey Harlin...we have used VHDL for so long we just haven't changed. When we evaluated assertions on the Palladium, we did use the "." as the separator...thanks!
I am using ncsim, Could you please tell me what is the syntax for forcing vhdl (RTL) signal from verilog testbench.