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vhdl-verilog interoperation ?

Can I force or probe a signal in vhdl module from verilog top testbench?
I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

Originally posted in cdnusers.org by hubertx

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archive over 18 years ago

hey Harlin...we have used VHDL for so long we just haven't changed. When we evaluated assertions on the Palladium, we did use the "." as the separator...thanks!

Originally posted in cdnusers.org by tom paulson
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archive over 18 years ago

hey Harlin...we have used VHDL for so long we just haven't changed. When we evaluated assertions on the Palladium, we did use the "." as the separator...thanks!

Originally posted in cdnusers.org by tom paulson
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