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vhdl-verilog interoperation ?

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Can I force or probe a signal in vhdl module from verilog top testbench?
I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

 


Originally posted in cdnusers.org by hubertx
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  • Hey, Tom!

    Also, in Palladium, once it goes through design import, there's no language difference (in reality, after HDLICE it's generally all verilog netlists). You can set the delimiterRule to verilog and then use '.' as hierarchical delimiter for the entire design. Using '.' is even more advantageous when you start with a gate-level netlist that usually contains instance names like '\a.b.c.d[0]_456' or the like. Those things get ugly real fast.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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  • Hey, Tom!

    Also, in Palladium, once it goes through design import, there's no language difference (in reality, after HDLICE it's generally all verilog netlists). You can set the delimiterRule to verilog and then use '.' as hierarchical delimiter for the entire design. Using '.' is even more advantageous when you start with a gate-level netlist that usually contains instance names like '\a.b.c.d[0]_456' or the like. Those things get ugly real fast.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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