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vhdl-verilog interoperation ?

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Can I force or probe a signal in vhdl module from verilog top testbench?
I heard some simulator has its own way to do that easily, can you give me a example to do that with ncsim?

 


Originally posted in cdnusers.org by hubertx
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  • Some of the more recent versions of IUS (ncsim) will take '.' as the hierarchical separator through a mixed language hierarchy. In older versions, you would have to guess at when to use '.' and ':' through a hierarchical reference.

    If you're not sure, bring up the design browser and scope down into the module you are interested in and the design browser will show you the hierarchical path with the appropriate delimiters.

    Let us know if this doesn't answer your question.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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  • Some of the more recent versions of IUS (ncsim) will take '.' as the hierarchical separator through a mixed language hierarchy. In older versions, you would have to guess at when to use '.' and ':' through a hierarchical reference.

    If you're not sure, bring up the design browser and scope down into the module you are interested in and the design browser will show you the hierarchical path with the appropriate delimiters.

    Let us know if this doesn't answer your question.

    Harlin!


    Originally posted in cdnusers.org by Harlinator
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