as C to Silicon external delay and working out all_inputs/outputs was not very clear I have put together a tcl script to set a default value for all.
35% on external on inputs & 75% on outputs relies on $clk_period for the moment.
Just thought I would post as search did not find much and might be useful for others.
Obviously lots of improvements could be done by making it a procedure, etc.
Thanks for posting this. That is a nice common utility function, so hopefully other C-to-Silicon Compiler users find it useful as well.
You might be interested to know that Stratus HLS provides a few different approaches to do this. The most common usage is as follows.
set_attr default_input_delay $input_delay_value
That attributes automatically set the input delays for all inputs, relative to the clock. (The clock is port is automatically excluded.)
There is a similar command for outputs... just substitute "output" for "input" above and in the examples below.
Stratus HLS supports multiple synthesis scenarios (a.k.a.configurations) in one project, meaning that there can be multiple implementations (with different synthesis options) for a given design. Often, the default input and output delays is the same for all scenarios, so the above still is the best practice.
But if you want to explicitly set default input and output delays for each configuration, you can do the following.
define_hls_config dut C1 --default_input_delay=$input_delay_value
define_hls_config dut C1set_attr default_input_delay $input_delay_value [find -hls_config C1]
Many attributes in Stratus HLS can also be set directly in your SystemC code, if you prefer that type of interface.
If that command (or directive) is in the module constructor, the specified delay will apply to all inputs of the module. If placed at the beginning of an SC_CTHREAD or SC_METHOD, then it apply just to that process.