Synthesis Area plus power estimate concatenation

Hi GioFz,

Which version of the tool are you using? You are redirecting the log output to a text file when using the report_power and report_gates -power commands using the TCL command  

set out [open "../rpt/blocks0001.rpt" w]

I would recommend that you use the

write_template 

command to write out the template command script that the tool comes with, this will help you with working out which commands

should work for the version of the tool you are using.

It would be best not to redirect the report commands to a file in the rpt directory initially and set the log file verbosity level to be 9, something like:

set_attribute information_level 9 /

This will increase the length of the tool log file but it will really help you in debugging things further.

What you can do as a quicker exercise is to create a new script that reads just one of the block netlist you are synthesizing back in to the tool and see if you can do

something like the following:

set_attribute information_level 9 /
set_attribute lib_search_path ../../libs
set_attribute library gf40.lib
read_netlist  block_0001005.vg
report_power
report_area
report_gates

That should tell you and you would be reducing your debug cycles for this.

Let's see how you get on, would be interesting to find out what is happening in your script.

J

Hi Jay Joshi,

Thank you for the good reply. Sorry I forgot to mention the version of the tool which is: Genus(TM) Synthesis Solution 16.22-s033_1 .

When I use report_power in my previous script I do  in this way  report_power $DESIGN  > ../rpt/report_gates_power_blocks0000.rpt  and for the following blocks I use the concatenated operator ">>" . The problem is that I get :  

**********log********************

Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [::report::power::report_power]
         : There is no unique design here.
          :Specify a design by using the cd command to change to that design's directory or specify the design as an argument for the command.
Failed on find_unique_design

*********************************

When I create the script you suggest, well, I get the three reports but the read_netlist  command seems to does not work (but it does not block the execution), so with or without I get the three report in the log. 
If I repeat for the second block I get always the "Failed on find_unique_design" .
I would like to highlight that I want only the dynamic power and the normalized (or un-normalized) area and not all the details that came from the reports.

G

Hi GioFz,

Seems like you have multiple designs in the tool when you run:

  Error : Multiple designs are available.  Specify the design you want to use. [TUI-17] [::report::power::report_power]          : There is no unique design here.           :Specify a design by using the cd command to change to that design's directory or specify the design as an argument for the command. Failed on find_unique_design  

You made progress! You should be able to change into the virtual directory called /designs that is in the tool and do and type ls in the script or command line of the tool shell to see the list of multiple designs in that

virtual directory.

You can replace the

read_netlist

command with the following multiple lines you had in the original script you showed us:

read_hdl -sv -library WORK ../vlog/blocks0001.v
set DESIGN block0001000
elaborate $DESIGN 
check_design -unresolved $DESIGN
set input_port_list { a } 
set output_port_list { y }  
synthesize -to_generic -effort high $DESIGN 
synthesize -to_mapped -effort high $DESIGN
set area_design [get_attribute area $DESIGN]
report_power 
report_area 
report_gates  

Do not use the >> concatenation command yet. We need to understand what is happening.

Did you take a look at the write_template command?

J

  Error : Multiple designs are available.

I get this error because when I try to have the report for another design. 
I used the write_template command and it is very nice, it seems useful thank you. But I think I did not explained my self well.

If I do the various report_power/ area etc. it works well, but I have different report files and more verbose than I need. As I said in the first post, I would need something very similar to my actual report:
-All the area results in one file
-All the power results in one file
In this way would be very easy to analyse them for my purposes.

( Take in account that I have many separate different blocks to synthesize and compare)

So if I do 

read_hdl -sv -library WORK ../vlog/blocks0001.v
set DESIGN block0001000
elaborate $DESIGN 
check_design -unresolved $DESIGN
set input_port_list { a } 
set output_port_list { y }  
synthesize -to_generic -effort high $DESIGN 
synthesize -to_mapped -effort high $DESIGN
set area_design [get_attribute area $DESIGN]
report_power 
report_area 
report_gates 




I get my various reports, but it is not what I want. 
Regards,
Giovanni

Hi GioFz,
Hmm....Adding the following to your synthesis script will help you read the tool log file as
a complete synthesis run without getting too lost in the tool log file :

set_attribute source_verbose true
set_attribute print_error_info true
set_attribute information_level 9 /

Maybe this little TCL procedure can guide you in the right direction:

#!bin/tclsh
#stackoverflow.com/.../incrementing-integer-value-stored-as-tcl-string
#
#
proc incr_block_name {name} {
 set digits [regexp -inline {\d+$} $name]
 set prefix [string range $name 0 end-[string length $digits]]
 set num [scan $digits %d] ;# prevents problems with invalid octal numbers 
 format "%s%0*d" $prefix [string length $digits] [incr num]
}

set BLOCK block0001000
for {set i 0} {$i < 11} {incr i} {
 
 puts "value of i inside first loop: $i"
 set DESIGN $BLOCK
 puts $DESIGN
 set BLOCK [incr_block_name $BLOCK]
}
#
#

value of i inside first loop: 0
block0001000
value of i inside first loop: 1
block0001001
value of i inside first loop: 2
block0001002
value of i inside first loop: 3
block0001003
value of i inside first loop: 4
block0001004
value of i inside first loop: 5
block0001005
value of i inside first loop: 6
block0001006
value of i inside first loop: 7
block0001007
value of i inside first loop: 8
block0001008
value of i inside first loop: 9
block0001009
value of i inside first loop: 10
block0001010

But what you really might want to do is create a bash script to go through each invocation of the synthesis tool automatically.
But I am confused as to what your naming convention is for file names - you read in ../vlog/blocks0001.v then set the DESIGN name
to be block0001000.

set_attribute source_verbose true
set_attribute print_error_info true
set_attribute information_level 9 /

set_attribute lib_search_path ../../libs
set_attribute library gf40.lib

read_hdl -sv -library WORK ../vlog/blocks0001.v

set DESIGN block0001000
set myra ra.$DESIGN.txt

elaborate $DESIGN 
check_design -unresolved $DESIGN
set input_port_list { a } 
set output_port_list { y } 
synthesize -to_generic -effort high $DESIGN 
synthesize -to_mapped -effort high $DESIGN
set area_design [get_attribute area $DESIGN]
report_power 
report_area > $myra

I created some file examples to show how you could easily grep for the results in a termial on a shell command line :

cat ra.block0001000.txt ra.block0001005.txt


 Gate Instances Area Library 
------------------------------------------
FD1QLLP 15 423.612 CORE9GPLL
FD1SQLLP 1 34.292 CORE9GPLL
HA1LL 14 254.167 CORE9GPLL
IVLLX05 2 8.069 CORE9GPLL
------------------------------------------
total 32 720.140





 Gate Instances Area Library 
------------------------------------------
FD1QLLP 15 400.612 CORE9GPLL
FD1SQLLP 1 37.292 CORE9GPLL
HA1LL 14 254.166 CORE9GPLL
IVLLX05 2 8.069 CORE9GPLL
------------------------------------------
total 32 700.139

grep total ra.* |tr : " " |sort -V -k4
ra.block0001005.txt total 32 700.139
ra.block0001000.txt total 32 720.140
ra.block0001002.txt total 32 723.139
ra.block0001004.txt total 32 723.139
ra.block0001001.txt total 32 723.140
ra.block0001003.txt total 32 723.140

There are two ways you can read in an environment variable
into the synthesis tool's TCL command shell assuming you are
using bash shell.

export blockname=block0000000
tclsh
puts $env(blockname)
puts $::env(blockname)

You could create a bash script like this:

1 #!/bin/bash
 2 for nameofblock in block0000000 block0000001 block0000002; do
 3 echo "Synthesizing $nameofblock hold on to your hat and stand back please";
 4 [[ "$version" =~ (.*[^0-9])$ ]] && version="${BASH_REMATCH[1]}$((${BASH_REMATCH[2]} + 1))";
 5 export blockname=$nameofblock
 6 ./mytool.bash
 7 done

./run.bash 
Synthesizing block0000000 hold on to your hat and stand back please
Thu 15 Feb 01:36:46 GMT 2018
This is to mimic Genus running
Thu 15 Feb 01:36:47 GMT 2018
finished block0000000
Synthesizing block0000001 hold on to your hat and stand back please
Thu 15 Feb 01:36:48 GMT 2018
This is to mimic Genus running
Thu 15 Feb 01:36:49 GMT 2018
finished block0000001
Synthesizing block0000002 hold on to your hat and stand back please
Thu 15 Feb 01:36:50 GMT 2018
This is to mimic Genus running
Thu 15 Feb 01:36:51 GMT 2018
finished block0000002


cat -n mytool.bash 
 1 #!/bin/bash
 2 echo `date`
 3 sleep 1
 4 ./mysynthtool
 5 echo "finished $blockname"

cat -n ./mysynthtool
 1 #!/usr/bin/tclsh
 2 puts "This is to mimic Genus running"
 3 puts [exec date]
 4 exec sleep 1

J

Thank you very much for the reply,

I will work on the information you gave me. However to clarify your confusion:

GioFz said:

read_hdl -sv -library WORK ../vlog/blocks0001.v

set DESIGN block0001000

elaborate $DESIGN
check_design -unresolved $DESIGN

set input_port_list { a }
set output_port_list { y }

synthesize -to_generic -effort high $DESIGN
synthesize -to_mapped -effort high $DESIGN

set area_design [get_attribute area $DESIGN]
set out [open "../rpt/blocks0001.rpt" w]
puts $out "Total gate_count $DESIGN : $area_design"
close $out

read_hdl -sv -library WORK ../vlog/blocks0001.v

set DESIGN block0001001

elaborate $DESIGN
check_design -unresolved $DESIGN

set input_port_list { a }
set output_port_list { y }

synthesize -to_generic -effort high $DESIGN
synthesize -to_mapped -effort high $DESIGN

set area_design [get_attribute area $DESIGN]
set out [open "../rpt/blocks0001.rpt" a]
puts $out "Total gate_count $DESIGN : $area_design"
close $out

.... and so on

***************************************************************

blocks0001.v  is a verilog file that contains 1000 modules . The first one is block1000 the last one is block1999 . For this reason the script reads from the same file and every time changes the $DESIGN, synthesize and the print the area on a file. If I do the same with the power I get 

GioFz said:

Error : Multiple designs are available. Specify the design you want to use. [TUI-17] [::report::power::report_power]
         : There is no unique design here.
          :Specify a design by using the cd command to change to that design's directory or specify the design as an argument for the command.
Failed on find_unique_design

Hi GioFz,

I am wondering if you have access to the documentation. No being impolite - just asking :-)

You can locate the PDF file in the installation directory of the tool or use the cdnshelp command
in a terminal window.

report power should have a design object that tell the tool where it is in the virtual design directory.

From the documentation :

You should be able to do the following by surrounding the report power command with the
virtual cd command that works in the synthesis tool.

cd /$DESIGN
report power
cd /

You could also use the TCL script I gave as a starting point to go through the design hierarchy that has the
1000 modules, and iterate over each one automatically in the loop just for the report power command.

Please do share more information - if you had explained that you had 1000 modules - we would have got here quicker! ;-)

Don't be shy to share information, especially if it will help us help you! :^)

J

Hi GioFz,

I am wondering if you have access to the documentation. No being impolite - just asking :-)

You can locate the PDF file in the installation directory of the tool or use the cdnshelp command
in a terminal window.

report power should have a design object that tell the tool where it is in the virtual design directory.

From the documentation :

You should be able to do the following by surrounding the report power command with the
virtual cd command that works in the synthesis tool.

cd /$DESIGN
report power
cd /

You could also use the TCL script I gave as a starting point to go through the design hierarchy that has the
1000 modules, and iterate over each one automatically in the loop just for the report power command.

Please do share more information - if you had explained that you had 1000 modules - we would have got here quicker! ;-)

Don't be shy to share information, especially if it will help us help you! :^)

J

Hi Jay Joshi,

Yes I have access to the documentation. So sorry for my silly errors about that. I said that I had a lot of blocks to synthesize but I was not accurate to say clearly that all these blocks are defined as modules in one verilog file.
I can understand that I was a little bit vague, however I was looking for a suggestion more than a problem solving. 
So, with all this information I could try to find a solution. 
By the way my initial request was about this :

"set area_design [get_attribute area $DESIGN]
set out [open "../rpt/blocks0001.rpt" w]
puts $out "Total gate_count $DESIGN : $area_design"
close $out"

Which result is 

"Total gate_count block0001000 : 18.522
Total gate_count block0001001 : 18.522
Total gate_count block0001002 : 18.8748
Total gate_count block0001003 : 18.8748 .....etc."

Every blockxxxxxxx  is a modules in the verilog file. So I get one line only for each modules. What I was trying to achieve is the same thing but with the POWER. So something like that:

"set power_design [get_attribute power $DESIGN]
set out [open "../rpt/blocks0001.rpt" w]
puts $out "Internal power $DESIGN : $power_design"
close $out"

"Internal power block0001000 : 1
 Internal power block0001001 : 2
 Internal power block0001002 : 3
 Internal power block0001003 : 4.....etc."

Simple in words but I think not so easy in practice. Although it is so easy to get the area and only the area ([get_attribute area $DESIGN]) but not the internal/dynamic power?

Thanks&regards,

GioFz

Thank you, it worked, I could troubleshoot using your suggestion. 

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