Synthesize net to flip-flop cell with differential output.

I have a digital block (SystemVerilog) that will eventually be placed into a larger AoT design. The connections between the analog and digital blocks need to be differential due to noise issues. I created a D flip-flop standard cell with a differential output (Q, nQ) that meets all the timing requirements of this design. This was characterized using Liberate and is now in the library I am using in Genus for synthesis.

Is it possible to configure Genus to synthesize specific output nets (by name) to this flip flop so that both Q and nQ are available in Innovus for P&R? If so, a link to the appropriate manual or documentation would be most appreciated - searching on the Cadence website hasn't revealed anything immediately useful.

Our previous method was to explicitly create both outputs in the HDL source and use HDL logic to ensure they were differential. This caused an additional inverter to be placed into the design which had a negative impact on timing. This method obviously does not scale to large designs and is somewhat bug-prone. Any better method would be appreciated.

Thanks for your help in advance!

The cell definition used in Liberate to generate the flip flop during characterization is shown below. It doesn't seem like Liberate is aware that Q and nQ are logically related but I was unable to find any option to define_cell that would achieve this.

set cell DFFC
if {[ALAPI_active_cell $cell]} {
    define_cell \
       -clock { CLK } \
       -async { nCLR } \
       -input { D } \
       -output { Q nQ } \
       -pinlist { CLK nCLR D Q nQ } \
       -delay delay_template \
       -power power_template \
       -constraint const_template \
       $cell
}