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RC gated clock - automatic insertion

guyra

Hi,

During the synthesis, the RC added gated clock on several gates, thus changed the attribute of the gate to " break_timing_paths = true".

I don't understand the reason for that, since I dont think there is a gated clock on this cell.

 

How can I debug this issue?

Is there a way to find out why the RC think this is a gated clock.

I tried to use the fanin command on this gate pins (all pins) and to check if one of the start point is gated clock, but I didn't find any thing..

Thx 

 

 

 

 

  •  Hi Guyra,

     this is usually do to clock_gating_checks. Most combo cells infer a clock gating check if a signal defined as clock drives one of the pins. This is not just RC but most tools out there behave that way. As a result of the clock_gating_check, the path needs to be segemented hence what you are seeing or sounds like it. If the questions is what gates infer clock gating checks and which do not, I am not sure but I belive things like muxes do not infer them. Be careful since a clock_gating_check violation is likely a real violation unless their is design knowledge not captured in the SDC constraints.

     

    good luck,

    gh-

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