constant propagation in RC

Hi all,

In some sub-modules there are some output ports which are assigned to a constant (e.g. assign OutPort1 = 1'b0 ). I expected that RC propagates these constants and removes the output ports from the sub-module interface. This should also be the case for the destination sub-module which receives this signal. For example in the following code I assume after synthesis RC removes the op1 and ip1 ports since they are constants:

sub1    i_sub1 (

                      .op1 (op),  // output op1 is assigned to zero in the sub1

                       .opX(X),

                       ....

                     );

sub2    i_sub2 (

                      .ip1 (op), 

                       .ipX(X),

                       ....

                     );

 Any idea why this does not happen?

Thank you for comments in advance!

Masoud