Our design instantced a lot designware and we always compare these designware with their behavior model when run FV with LEC. This method always works, only except DW02_multp and some other designware. So, we'll blackbox these designware to pass the FV. But as DC do a lot of optimization to DW02_multp's input and output pins, while we must set constraints accordingly. These constraints lead to so many troubles to us as our design changes or re-synthesize. I was wondering if there is any way we also can compare DW02_multp without any blackboxes set. Thanks!
There is a solution article that you can check out...
Titled "How to avoid false NEQs while comparing Synopsys DesignWare DW02_mult_n_stage and DW_*_pipe?"
(or with this URL below)
You need special treatment to verify some DW modules. You must use the ANALYZE MODULE command when verifying DW02_multp to avoid getting false noneq
analyze module *DW02_multp* -partial_sum_outputs -golden -replace