Stats

  • Locked Locked
  • Replies 7
  • Subscribers 63
  • Views 18279
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

annotating switching activity

alexsieh

Dear fellows,

 Please shine some light in how I should annotate switching activity with TCF properly.

I used "dumptcf -internal" to create a tcf file from my testbench simulation. I did not set any scope, so the tcf file annotates all of the switching activites of my DUT and of my testbench. Thats ok rite? I am assuming the RTL Compiler will ignore the switching activity recorded from my testbench and use only the numbers regarding the DUT instances. After I read the tcf file in RC and synthesize my DUT, I noticed that in the power report, some negative numbers came out.

Question1. Why does Cadence allow negative dynamic power in its report? Does it make sense?

Then, I generated tcf files using "dumptcf -internal -scope .." to each hierachical instance of my DUT. In RC, I performed multiple commands "read_tcf ...", but the numbers do not add to what the non-scoped tcf file first gave me. The power analysis came out to be much lower even though I read the tcf files of each DUT instance.

Question2. Can i have RTL Compiler make multiple tcf reads? Does it override the previous read tcf?

Hope yall can help me! Sincerely,

Alex

  • johannes

    Hi Alex,

    1. I never saw negative numbers in a power report before. Do you have any special IPs with customized lib-files in your design? Any other "special" library? I would try to do more analysis on the parts, where you see the negative numbers. I would even go down to cell level, and try to re-calculate what exactly happens (net capacitance, pin capacitance etc.). Do you get 100% TCF coverage on the sequential outputs after reading the TCF?

    2. Yes, you can use several read_tcf. It will overwrite only the toggles, which are redefined, and keep the others. You can also use "read_tcf -update", which will then combine the TCFs (i.e. not overwrite anything), where you can even give different weights using "-weight". I assume, you are using the "-instance" switch, in order to determine the scope, right? Also here: Do you get 100% TCF coverage?

    Regards,
    Johannes

     

  • grasshopper

    Hi Alex,

    issue #1 sounds like a bug to me - what version of RC are you using. Is the TCF also negative or not. Sounds like TCF is bad with negative toggle counts propagating through the flow or there is some issue on RC side of the fence. I suggest you try recent release and report to the forum.

    issue #2 is supported as Johnnes mentioned. This is documented in quite some detail on the Low Power User Guide in the documentation. Generally speaking, last activity read / applied to a node wins. So if you read 2 TCF files that have one register overlap, then the activity on the last file wins. In addition, there are several options and switches to do this in a structured way.

    regards,

    gh

  • alexsieh
    Hi everybody, sorry for the taking so long.

    Thanks everybody for your help

    I have RTL Compiler v07.10-p004_1 (64bits), so I will have to update it.

    I do not have customized or special lib-files. There are all standard digital cmos.

    Unfortunately, the TCF coverage is not 100%, but I set lp_power_analysis_effort to high, so that I propagate the switching activity.

    What should be a good target number for a TCF coverage? Are power vectors suppose to be much different from the functional vectors? I believe I dont get 100% TCF coverage because my power vectors are not complete.

    I decided to generate only one tcf for the entire design, because it is easier. So I used dumptcf -internal -scope testbench.top.

    Now, I do not have to worry about the issue of reading multiple tcf files. Thank you for the explanation regarding the command. I will remember to use read_tcf -update next time.

    After reading the tcf file, the RC gives out the following summary:

    Nets/Pins asserted in TCF file : 5312
    Total Nets/Pins in TCF file    : 6514
    -------------------------------------------------------
    Asserted Primary inputs in design              : 260 (100.00%)
    Total connected primary inputs in design       : 260 (100.00%)
    -------------------------------------------------------
    Asserted sequential outputs          : 710 (100.00%)
    Total connected sequential outputs   : 710 (100.00%)
    -------------------------------------------------------
    Total nets in design                 : 20349 (100.00%)
    Nets asserted                        : 11795 (57.96%)
    Clock nets                           : 0 (0.00)
    Constant nets                        : 675 (3.32)
    Net does not have activity asserted  : 8554 (42.00%)
    -------------------------------------------------------



    Sincerely,
    Alex Sieh
  • johannes

    Hi Alex,

     

    As long as you have 100% coverage on sequential outputs, which you have, it's perfectly fine.

     

    Regards,

    Johannes

  • alexsieh
    Hello everyone,

    I have 100% coverage on sequential outputs, so I am on the right track.
    I also upgraded RC to the lastest version and the TCF net coverage went up as well.
    Thank you for your answers. I really appreciate every input.

    A quick RC question please.
    If I use a different process technology, will the RC area report change in terms of GEs?

    For instance, if I use the same RTL code, the same constraints (same clock), but use another process tech, will the number of cells (GEs) change?

    I cannot verify this on my own through RC report, because I don't have the new process tech library.
    We are still investigating about adopting a newer process technology. I am guessing the circuit will be synthesized basically in the same way since I have the same constraints. So the number of cells ought to be closely the same.

    Thanks & Regards,
    Alexander Sieh
  • grasshopper

     Hi Alex,

     not sure what GE stands for but different libraries lead to potentially different optimizations lead to potentially different area, cell count, performance, power, etc. For example, faster cells could result in a different architecture used for an adder which requires vastly different resources

     

    gh-

  • alexsieh
    Ok... Thanks

    GE meaning Gate Equivalent.
    A tech library usually defines GE to be its smallest standard cell (for example, a NAND2x1).
    Then, the physical area of the other standard cells (like AOI2x1, flip-flop, etc) can be given in terms of GEs.

    area of NAND2x1 == 1 GE
    area of AOI2x1    == 12.5 GEs


    Sincerely,
    Alexander Sieh

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.