synopsys designware can not be compiled in the conformal Equivalence

I’m assuming the netlist is from DC.

A rule of thumb for Conformal family tools (e.g. LEC) is models must be synthesizable. Conformal can handle most DW models used by our customers. DW_div_seq.v, as provided by Synopsys, is not synthesizable due to clock style in the code. If the modules boundaries are preserved in the golden and revised design then black boxing (via add translate module) is one solution. If the boundaries are not preserved, one can use a replacement flow described in the SourceLink document: 11175800. (Go to http://sourcelink.cadence.com and search for the document number. There is also a highly recommended application note on Conformal and DW available from your AE.) Since the original Verilog model is not synthesizable the DW_div_seq module will not be verified with either of these techniques. Also, it is always a good idea to use simulation models that match the release of your synthesis tool.

For completeness I’m including information on synopsys translate_off/on but it appears you have already taken care of that. Most DW models have synopsys translate_off/on pragmas surrounding functional model code. To read the code one can use:

set directive off translate_off translate_on -file DW*

This is described in the SourceLink solution 11175794.

If you are using an RC netlist and models then you should be able to completely verify the code for this model (as well as many others).

Also a new a new method for handling DW is available with 8.1. Please contact an AE for details or attend the “Back to School” 8.1 updates being rolled out world-wide.

If you need guidance with any of the information, please contact a Cadence support AE by filing a Support Request (SR):

http://sourcelink.cadence.com

-Noel

I’m assuming the netlist is from DC.

A rule of thumb for Conformal family tools (e.g. LEC) is models must be synthesizable. Conformal can handle most DW models used by our customers. DW_div_seq.v, as provided by Synopsys, is not synthesizable due to clock style in the code. If the modules boundaries are preserved in the golden and revised design then black boxing (via add translate module) is one solution. If the boundaries are not preserved, one can use a replacement flow described in the SourceLink document: 11175800. (Go to http://sourcelink.cadence.com and search for the document number. There is also a highly recommended application note on Conformal and DW available from your AE.) Since the original Verilog model is not synthesizable the DW_div_seq module will not be verified with either of these techniques. Also, it is always a good idea to use simulation models that match the release of your synthesis tool.

For completeness I’m including information on synopsys translate_off/on but it appears you have already taken care of that. Most DW models have synopsys translate_off/on pragmas surrounding functional model code. To read the code one can use:

set directive off translate_off translate_on -file DW*

This is described in the SourceLink solution 11175794.

If you are using an RC netlist and models then you should be able to completely verify the code for this model (as well as many others).

Also a new a new method for handling DW is available with 8.1. Please contact an AE for details or attend the “Back to School” 8.1 updates being rolled out world-wide.

If you need guidance with any of the information, please contact a Cadence support AE by filing a Support Request (SR):

http://sourcelink.cadence.com

-Noel