LEC Issue with falling edge clock gater cells

Hi,

I am doing a comparison between my RTL and the corresponding netlist.
The original RTL doesn't have any clock gaters instantiated. During synthesis clock gater cells of the library ared added.
Two types of clock gater cells are used:

• Rising edge clock gater cell (Latch transparent on low level of clock + AND gate)
• Falling edge clock gater cell (Latch transparent on high level of clock + OR gate)

Rising edge clock gater cell is used for DFFs clock on rising edge of the clock.
Falling edge clock gater cell is used for DFFs clock on rising edge of the internal inverted clock.

LEC doesn't manage to match RTL vs netlist, when falling edge clock gater cells are added.

However, when I replace falling edge clock gater cells by rising edge clock gater cells in the netlist, all is OK and the RTL matches the netlist.

I use "set flatten model -gated_clock" command.

How to fix this problem ? 

Thank you in advance
Frederic