Unit names for vhdl and verilog

Hi!

I have some trouble with the case senstivity of unit names in desing libraries of IUS 8.2. Up to now the design has only source files in vhdl and everything went fine. But now i had to import verilog files from a netlist generator for verifying timing delays. This results in doubeling of unit names, due to the case sensitivity in verilog and the insensitivity in vhdl.

for example:

vhdl design:

entity newLogicCircuit is
port ( xyz: std_logic; );
end newLogicCircuit;

verilog imported file for timing simulation:

module newLogicDesign (xyz);
input xyz;
...
endmodule

Resulting trouble in compiled library:

newLogicDesign
    module

newlogicdesign
   entity
   behaviour

What I would like to have is one unit in library with all views for this unit within one unit only not in two seperate ones, because they all belong together.

Currently the only way to do this is writing all unit names in lower case in vhdl, resulting in generated lower case names in verilog as well. But this makes this names rather hard to read, because its hard to seperate each word.

For ncvlog there exists a special command line option (- upcase) which can force every verilog name to be compiled as upper case name into working library. That doesn't helps with this issue because all vhdl units are converted to lower case, but maybe there exists a way to force every verilog name to lower case. However I havn't found such a option.

Does somebody know a solution or workaround for that issue?

Regards,

Thomas