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Synthesizing Mixed Verilog-VHDL in RTL Compiler?

Scrivner

Does anyone have experience using RTL Compiler with a design that includes mixed Verilog and VHDL code? I will have a design soon that is verilog at top level with some small verilog modules instantiated, but the bulk of the design will be an instantiation of a large VHDL hierarchy.

Is it as simple as creating an instantiation of the VHDL module in the top level verilog and then reading in all of the RTL into RC? Or are there some tricks that I'll need to know? Any special switches in RC that I should know about for mixed Verilog-VHDL synthesis?

 Thanks in advance for any help anyone can provide!

Bart 

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  • Hi Bart,

    I have worked on several mixed RTL designs and despite me not liking VHDL I cannot say RC cared one way or another. There are certainly more nuances with VHDL than Verilog but none of them have much to do with the mixed language characteristics of the design. Simply ensure that the blocks are read in the correct read_hdl block and you should be ok. Not sure how much VHDL you have done in RC but their are some order depndancies (i.e reading architecture and entity in right order, etc.) so make sure you read things in the right order. Also remember the -library switch when reading HDL so thing go to the right libraries. Most attribute that may have an impact start with hdl or vhdl so usual

    get_attr -h *hdl_*  * 

    would provide most attribute that may be of interest to you

     good luck,

    gh-

Reply

  • Hi Bart,

    I have worked on several mixed RTL designs and despite me not liking VHDL I cannot say RC cared one way or another. There are certainly more nuances with VHDL than Verilog but none of them have much to do with the mixed language characteristics of the design. Simply ensure that the blocks are read in the correct read_hdl block and you should be ok. Not sure how much VHDL you have done in RC but their are some order depndancies (i.e reading architecture and entity in right order, etc.) so make sure you read things in the right order. Also remember the -library switch when reading HDL so thing go to the right libraries. Most attribute that may have an impact start with hdl or vhdl so usual

    get_attr -h *hdl_*  * 

    would provide most attribute that may be of interest to you

     good luck,

    gh-

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