Synthesizing Mixed Verilog-VHDL in RTL Compiler?

Does anyone have experience using RTL Compiler with a design that includes mixed Verilog and VHDL code? I will have a design soon that is verilog at top level with some small verilog modules instantiated, but the bulk of the design will be an instantiation of a large VHDL hierarchy.

Is it as simple as creating an instantiation of the VHDL module in the top level verilog and then reading in all of the RTL into RC? Or are there some tricks that I'll need to know? Any special switches in RC that I should know about for mixed Verilog-VHDL synthesis?

 Thanks in advance for any help anyone can provide!

Bart