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CadenceRC area report

Hava

 Hi, I've got a area report for my design.

  Gate    Instances   Area      Library  
------------------------------------------
FD1QLLP        15  423.612    CORE9GPLL
FD1SQLLP       1   34.292    CORE9GPLL
HA1LL            14  254.167    CORE9GPLL
IVLLX05           2    8.069    CORE9GPLL
------------------------------------------
total                32  720.140   

Could anyone tell me what measurement is used to get the area number (associating with each type of gates)? And how can I transfer this area  result into NAND count respectively? Thanks~

  •  Hava,

         The area reported in the report is based on the area numbers in the library. The easiest way to figure out the NAND2 equivalent is to run report gates and look for the area of the smallest NAND2 in that report. Then divide the reported total area by that NAND2 area and you have your answer.

     -Jeff-

  • Hi, Jeff,

    Thanks to your answer now I have the idea.But I don't understand how to run report gates. Since I have the amount of gates and total area of each type, I can get the average area of each type of gate by simple division. But I don't know how to know the area of the smallest NAND2. BTW,  NAND2 gates have different areas?Couldyou explain me, I'm totally a newbie here......Thank you .

  • Hava,

    Let's try a quick example:

     rc:>report area

     
    ============================================================

      Generated by:           Encounter(R) RTL Compiler v09.10-s125_1

      Generated on:           Sep 30 2009  06:50:55 AM

      Module:                 ihalu

      Technology library:     corelib_p_wc 3.0

      Operating conditions:   _nominal_ (balanced_tree)

      Wireload mode:          enclosed

      Area mode:              timing library

    ============================================================

     
    Instance        Cells  Cell Area  Net Area   Wireload    

    -----------------------------------------------------------------

    ihalu                    172       4801         0        50K (S)

      addinc_add_165_28_1     16       1114         0        50K (S)


     (S) = wireload was automatically selected


    rc:> report gates

     
    ============================================================

      Generated by:           Encounter(R) RTL Compiler v09.10-s125_1

      Generated on:           Sep 30 2009  06:50:46 AM

      Module:                 ihalu

      Technology library:     corelib_p_wc 3.0

      Operating conditions:   _nominal_ (balanced_tree)

      Wireload mode:          enclosed

      Area mode:              timing library

    ============================================================

     Gate    Instances    Area       Library    

    -----------------------------------------------

    an2x05pd           1    16.384    corelib_p_wc

    ao1nx2pd           1    28.672    corelib_p_wc

    ao2anx2pd          2    65.536    corelib_p_wc

    ao2pd             15   368.640    corelib_p_wc

    ao30npd            1    36.864    corelib_p_wc

    ao35pd             1    28.672    corelib_p_wc

    ao36pd             1    32.768    corelib_p_wc

    ao37apd           15   491.520    corelib_p_wc

    ao4apd             1    28.672    corelib_p_wc

    ao7apd             2    49.152    corelib_p_wc

    ao7nx2pd           1    24.576    corelib_p_wc

    aos32pd            2    49.152    corelib_p_wc

    aos3pd            30   737.280    corelib_p_wc

    aos6pd             1    16.384    corelib_p_wc

    df1pd              1    53.248    corelib_p_wc

    df1qpd             5   225.280    corelib_p_wc

    fa1x2pd           16  1114.112    corelib_p_wc

    ivpd               1     8.192    corelib_p_wc

    ivx05pd            1     8.192    corelib_p_wc

    ivx3pd             2    24.576    corelib_p_wc

    mx41pd             1    57.344    corelib_p_wc

    nd2ax05pd          1    16.384    corelib_p_wc

    nd2x05pd          20   245.760    corelib_p_wc

    nd2x2pd            2    40.960    corelib_p_wc

    nd4x05pd           1    20.480    corelib_p_wc

    nds2apd            1    16.384    corelib_p_wc

    nr2ax05pd         19   311.296    corelib_p_wc

    nr2x05pd           1    12.288    corelib_p_wc

    nr2x2pd            2    40.960    corelib_p_wc

    nr3x05pd           1    16.384    corelib_p_wc

    nr4x05pd           3    73.728    corelib_p_wc

    nrs2x2pd           1    20.480    corelib_p_wc

    or2x2pd            2    32.768    corelib_p_wc

    or3ax2pd           1    28.672    corelib_p_wc

    xn2x2pd           16   458.752    corelib_p_wc

    -----------------------------------------------

    total            172  4800.512                


    Type    Instances   Area   Area %

    -------------------------------------

    sequential         6  278.528    5.8

    inverter           4   40.960    0.9

    logic            162 4481.024   93.3

    -------------------------------------

    total            172 4800.512  100.0

    Now look at the cells called nd2* (making the assumption that these are indeed the NAND2 gates). Find the smallest one and that is one you are looking for. Now divide the total by that.


    -Jeff-

  •  Hi Jeff,

    I noticed that we are using different technology library, mine is CORE9GPLL, this doesn't affect the NAND2 equivelant? I am looking for a library that can show the area number of a smallest NAND but so far I have nothing.Do you know if there is a way to know the area info of a NAND without running a syn?  

  • You can certainly look in the .lib file if you have it. For example:

    cell(nd2x05pd) {

    ......

    area: 12.288

    .....

  •  Thankyou Jeff, I found the .lib file and there I found a NAND gate which is 6 um2 finally.

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