Verilog Netlist to VHDL Netlist?

If you do a google search you'll get some hits for various Verilog to VHDL conversion programs. I don't have any personal experience to tell you which ones might work and which ones wouldn't.

 I do deal with SDF annotation of gate level models in both VHDL and Verilog on a regular basis, so I can say that it does work well regardless of target language. But changing between the two is not going to be trivial. Perhaps the two biggest concerns I can think of without knowing your design process, are the provision of VITAL timing models for your VHDL gates and the different naming conventions between the two languages. Do you already have VITAL VHDL models for your gate level circuit? Was the SDF file created with the same VHDL naming conventions that the conversion program will be using?