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Reg .VCD file generation

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Hi,

 

   I need to run power analysis . so i need  .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need some steps....i asked in digital forum they requested me to post here... i.e in this forum...

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  • I realize that it is frustrating when everyone tells you to look somewhere else. But I can't tell you how to create a VCD file here if you are using Modelsim to simulation your netlist. This is a Cadence user's forum. If you were using Cadence's NC-Verilog or NCVHDL, you would create a VCD file using a TCL command on the simulator's interface.

     

    database -open -vcd testpatterns.vcd
    probe -all -depth all

     

    But I wouldn't know what commands you would use in Modelsim, since it is produced by another company.

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  • I realize that it is frustrating when everyone tells you to look somewhere else. But I can't tell you how to create a VCD file here if you are using Modelsim to simulation your netlist. This is a Cadence user's forum. If you were using Cadence's NC-Verilog or NCVHDL, you would create a VCD file using a TCL command on the simulator's interface.

     

    database -open -vcd testpatterns.vcd
    probe -all -depth all

     

    But I wouldn't know what commands you would use in Modelsim, since it is produced by another company.

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