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Constraint two path in the design to have equal propagation delay

Hi all,

How to contraint two path in the design to have equal propagation delay using SDC file in RTL compiler? For example, is there a way to specify in RTL compiler to make path point A to point B have equal propagation delay as path point A to point C in the design?

Thanks for your time.

Regards.

grasshopper over 15 years ago

Hi diablo,
The SDC command set_data_check is the the constraint that you are looking for. Unfortunately, it is not supported in RC today so you will have to resort to alternative workaround such as using set_max_delay/path_delay
hope this helps,
gh-
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diablo over 15 years ago

Thanks gh. I will try using path_delay.
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Genky over 15 years ago

Hi,
Is this command(set_data_check) still not supportted?
Genky
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