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constraint file

my screen
Hi I am new to cadence software and i would like to know How to write a constraint file for Area and Timing constraints for a simple design (AND gate)
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  • Hi My Screen,

    it is hard to come up with one size fits all constraints. Generally speaking you will need to do the following in SDC syntax

     

    (1) deifne clock nets and/or virtual clocks

       create_clock -period 10.0 [get_ports <port name>

    (2) Define input and output delays as well as clock references

       set_input_delay...

       set_output_delay...

     (3) Specify any timing exception

      set_multicycle_path...

      set_false_path...

    As far as area is concerned, most modern synthesis tools will always try to minimize area within the timing and power constraints provided so nothing special needed there.

    The RTL compiler installation contains a document on timing analysis and there are many example of SDC constraints on the web. 

     Just out of curioisy, why are you synthesizing a single AND gate. Is there any reason why you would not expect, you guessed it, and AND gate or its NOR equivalent if faster/smaller. Seems like a puzzling use of a synthesis tool.

    hope this helps,

    gh-

     

Reply

  • Hi My Screen,

    it is hard to come up with one size fits all constraints. Generally speaking you will need to do the following in SDC syntax

     

    (1) deifne clock nets and/or virtual clocks

       create_clock -period 10.0 [get_ports <port name>

    (2) Define input and output delays as well as clock references

       set_input_delay...

       set_output_delay...

     (3) Specify any timing exception

      set_multicycle_path...

      set_false_path...

    As far as area is concerned, most modern synthesis tools will always try to minimize area within the timing and power constraints provided so nothing special needed there.

    The RTL compiler installation contains a document on timing analysis and there are many example of SDC constraints on the web. 

     Just out of curioisy, why are you synthesizing a single AND gate. Is there any reason why you would not expect, you guessed it, and AND gate or its NOR equivalent if faster/smaller. Seems like a puzzling use of a synthesis tool.

    hope this helps,

    gh-

     

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