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Help: memory equivalence check between RTL and schematic

WorldMaker

Hi,

It mentions that encounter conformal equivalence checker can do memory equivalence check between schematic and RTL, but I cannot any example or demo. Is there anyone can demo how to do memory EC? I am wondering how the EC engine deal with the bit-cell array, treating it as black box and ignoring it? or the EC engine abstract the bit-cell schematic into latch and compare the abstracted memory verilog with the memory primitive?

Can the replica bit-line style memory be checked by EC?

thanks,

Worldmaker

Parents

  • Hi Sean,

    I am trying to check the equivalence between the schematic and the RTL simulation model for custom memories which has testing logic designed inside (traditionally, we model the ram as flop in RTL simulations). As you mentioned, Conformal GXL can generate a verplex memory model which is actually the memory core using the GXL memory primitives. Now we can build a wrapper model which instances the generated verplex model and the testing logic. Can Conformal GXL check the equivalence between the wrapper model and the RTL simulation model? If yes, both the memory core and testing logic are verified. If not, can the testing logic be verified seperately by black boxing the memory core?

    Could you please demo a "dofile" which can fulfil the task or point me to somewhere where I can find some similar demos? I cannot log onto the sourcelink now, and thus I cannot check if there are similar demos on sourcelink.

    Here is an example RTL simulation model for a dual port SRAM:

    /////////////////////////////////////////////////////////////////////

    module mem2p (wclk,wadr,wdin,rclk,radr,rdout);

    parameter adrbits=7;

    parameter databits=8;

    parameter adrmax = (1<<adrbits)-1;

    input wclk;

    input [adrbits-1:0] wadr;

    input[databits-1:0] wdin;

    input rclk;

    input [adrbits-1:0] radr;

    output[databits-1:0] rdout;

    reg[databits-1:0] rdout;

    reg[databits-1:0] mem[0:adrmax];

    always @(negedge wclk) mem[wadr] = wdin;

    always @(posedge rclk) rdout=mem[radr];

    endmodule

Reply

  • Hi Sean,

    I am trying to check the equivalence between the schematic and the RTL simulation model for custom memories which has testing logic designed inside (traditionally, we model the ram as flop in RTL simulations). As you mentioned, Conformal GXL can generate a verplex memory model which is actually the memory core using the GXL memory primitives. Now we can build a wrapper model which instances the generated verplex model and the testing logic. Can Conformal GXL check the equivalence between the wrapper model and the RTL simulation model? If yes, both the memory core and testing logic are verified. If not, can the testing logic be verified seperately by black boxing the memory core?

    Could you please demo a "dofile" which can fulfil the task or point me to somewhere where I can find some similar demos? I cannot log onto the sourcelink now, and thus I cannot check if there are similar demos on sourcelink.

    Here is an example RTL simulation model for a dual port SRAM:

    /////////////////////////////////////////////////////////////////////

    module mem2p (wclk,wadr,wdin,rclk,radr,rdout);

    parameter adrbits=7;

    parameter databits=8;

    parameter adrmax = (1<<adrbits)-1;

    input wclk;

    input [adrbits-1:0] wadr;

    input[databits-1:0] wdin;

    input rclk;

    input [adrbits-1:0] radr;

    output[databits-1:0] rdout;

    reg[databits-1:0] rdout;

    reg[databits-1:0] mem[0:adrmax];

    always @(negedge wclk) mem[wadr] = wdin;

    always @(posedge rclk) rdout=mem[radr];

    endmodule

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