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Help: memory equivalence check between RTL and schematic

WorldMaker
WorldMaker over 15 years ago

Hi,

It mentions that encounter conformal equivalence checker can do memory equivalence check between schematic and RTL, but I cannot any example or demo. Is there anyone can demo how to do memory EC? I am wondering how the EC engine deal with the bit-cell array, treating it as black box and ignoring it? or the EC engine abstract the bit-cell schematic into latch and compare the abstracted memory verilog with the memory primitive?

Can the replica bit-line style memory be checked by EC?

thanks,

Worldmaker

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  • archive
    archive over 15 years ago
    Hi WorldMaker, Yes, you should be able to compare two RTL designs, using Conformal equivalency checker. However, this depends on whether two designs have similar structure - ie logic cone at all end points has to match cycle by cycle. I would recommend black boxing the core memory array in both, and make sure the wrapper logic is equivalent. As for the documentation or demo, it's available at sourcelink, as well as the full documentation at Conformal installation/doc directory. Please contact myself or your Cadence contact and see if you can get a hold of one of the above. You can email me at 'surlung@cadence.com' Thanks, Sean
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  • archive
    archive over 15 years ago
    Hi WorldMaker, Yes, you should be able to compare two RTL designs, using Conformal equivalency checker. However, this depends on whether two designs have similar structure - ie logic cone at all end points has to match cycle by cycle. I would recommend black boxing the core memory array in both, and make sure the wrapper logic is equivalent. As for the documentation or demo, it's available at sourcelink, as well as the full documentation at Conformal installation/doc directory. Please contact myself or your Cadence contact and see if you can get a hold of one of the above. You can email me at 'surlung@cadence.com' Thanks, Sean
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