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Encounter Write_sdf generate error with Modelsim

rv01

Hi after having completed the P&R with timing optimization with SOC Encounter, 

we generated the .sdf for simulation with ModelSim.

We are receiving this error message after we use write_sdf command under Encounter

# ** Error: (vsim-SDF-3262  Failed to find matching specify timing constraint.

We try using write_sdf with "-version 2.1" and still get the same error message

Does any one have any hint what would be causing this issue

Thanks
r-v


Parents

  • This looks like it might be a Modelsim error message so you may need to go to one of their forums to learn how to interpret it.

    In general, though, we can say that any SDF annotation record must have a matching line in the Verilog source code. If your SDF file has "(SETUP...", there has to be a $setup task in the Verilog source code. If your SDF file has "(IOPATH i o..." there has to be a "( i => o ) = (..." line in your module's specify block. Everything has to match *exactly* before the annotation will take place.

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  • This looks like it might be a Modelsim error message so you may need to go to one of their forums to learn how to interpret it.

    In general, though, we can say that any SDF annotation record must have a matching line in the Verilog source code. If your SDF file has "(SETUP...", there has to be a $setup task in the Verilog source code. If your SDF file has "(IOPATH i o..." there has to be a "( i => o ) = (..." line in your module's specify block. Everything has to match *exactly* before the annotation will take place.

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