LEC between a posedge DFF and a low-pass D latch followed by a posedge D flop

Hi all,

There are two flops which should be equivalent, but Conformal reported an unmapped latch and a non-equivalent DFF. The 1st flop is a posedge D flop described by "always @(posedge CLK)" statement, and the 2nd flop is comprised of a low-pass D latch which is followed by a posedge D flop and the clock of the latch and flop is shorted.

My question is: How to remove the unmapped latch and fix the non-equivalent DFF? Should I delete the compared DFF using command "delete compared points DFF_reg" ?  The verilog of the two flops and the dofile are shown as follows:

////////////////verilog of the1st flop (DFF_a.v)///////////////

module dff (CLK,D,Q);
input  CLK;
input  D;
output Q;
reg    Q;

always @(posedge CLK)
  Q <= D;
endmodule

////////////////verilog of the 2nd flop (DFF_b.v) /////////////// 

module dff (CLK,D,Q);
input  CLK;
input  D;
output Q;
reg    Q;
reg    LAT;

always @(CLK or D) begin
if (~CLK) LAT <= D;
end
always @(posedge CLK) begin
Q <= LAT;
end
endmodule

 /////////////////////dofile//////////////////

read design DFFa.v -gol

read design DFFb.v -rev

go

////////////////////////////////////////////////

If the 1st flop is changed to the combination of a low-pass and high-pass d latch and the 2nd flop is unchanged. In this case, both of the two flops has two primary output pins: LAT, Q. 

Similarly, there are also unmapped and non-equivalent points, and how to verify the two flops? Verilog files of the two flops are as belows:

//////////////////verilog of the 2nd flop (DFF_c.v) ////////////////  

module dff (CLK,D,Q,LAT);
input  CLK;
input  D;
output Q;

output LAT;
reg    Q;

reg LAT;

always @(CLK or D) begin
if (~CLK)  LAT <= D;

if (CLK) Q <=LAT;

end
endmodule

////////////////verilog of the 2nd flop (DFF_d.v) /////////////// 

module dff (CLK,D,Q,LAT);
input  CLK;
input  D;
output Q;

output LAT;
reg    Q;
reg    LAT;

always @(CLK or D) begin
if (~CLK) LAT <= D;
end
always @(posedge CLK) begin
Q <= LAT;
end
endmodule

Thanks,

Justin