I have been trying to get my RC synthesized Verilog code (which contains some basic/cds_thru blocks) to pass LVS and DRC with no luck. it seems that DRC will never allow me to have conflicting labels/pins on the same net, So:
I used removeDevice() in LVS rules to short the pins in the schematic view but still the number of terminals mismatches in LVS! I need something in the layout to indicate that, for example, vdd! and output<3> are shorted. If I try to just label vdd or add another pin then DRC and extraction fails, therefore, LVS fails.
I am just using NCSU CDK 1.6 bet.
I have seend solution id 1839474 but that does not fix my problem.