RTL design

 I have 2 FF which called FF_A and FF_B. FF_A is clocked by clock_A and FF_B is clocked by clock_B. Clock A is the source clock and clock B is the divided by 2 clock. Because both FF_A and FF_B both belongs to the same clock domain, so i need not insert any synchronizer between these 2 FF. At the later stage, i want to set the following constrains in RC and ETS.

#fast to slow domain: skip every other data launch
dc:set_multicycle_path -setup 2 -from [get_clock clock_A] -to [get_clock clock_B] -start
dc:set_multicycle_path -hold  1 -from [get_clock clock A] -to [get_clock clock_B] -start

 But i don't know how can i write the correct RTL to fulfill above setting in RC and ETS. Or it is no special consideration during RTL design. Please give me some comments.Thanks a lot