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Recursive coding in verilog

gchalive

Is is possible to instantiate a module recursively in verilog.

I understand that there can be recursive functions but how about

behavioural modelling of a component using recursion.

How does the synthesis tool handle this??

Parents

  •  Hi gchalive,

    general rule of thumb is that provided that the constructs are legal, synthesizable and the recursion can be determined at compile time, it is accepted by many tools. All of that being said, I would not quite describe recursive programming as a great technique for creating RTL since your hardware better be known at compile time which means that there is limited need for the recursion.

     just my 2c,

    gh-

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  •  Hi gchalive,

    general rule of thumb is that provided that the constructs are legal, synthesizable and the recursion can be determined at compile time, it is accepted by many tools. All of that being said, I would not quite describe recursive programming as a great technique for creating RTL since your hardware better be known at compile time which means that there is limited need for the recursion.

     just my 2c,

    gh-

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