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  3. Gate mapping in RC

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Gate mapping in RC

gchalive
gchalive over 15 years ago

 Hi there.

 Is there any attribute to set in cadence RC which prevents from mapping a function to a different gate implementing a different function.

For example I dont want it to program a nand gate to implement an inverter by tying one of the inputs to 1. 

Thanks

gchalive

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  • grasshopper
    grasshopper over 15 years ago

     Hi gchalive,

     I am curious what your exact requirement. What your describing on combinational cells makes limited sense since ultimately your HDL would have to be excruciatingly detailed to ensure 1:1 correspondance exist to every combo structure in your design. Say

     

    assign a = b || c || d || e && f && !g

    could map to a large number of permutations hence why you let the synthesis tools decide the optimal one

    There are controls in RC for exact mapping of flops and to limit mapping of specific HDL constructs but ultimately the question is why should you need to do any of that. RC will only map an inverter the way you described earlier if it provided a QoR benefit. Otherwise, there is no reason RC would not pick the inverter.

     regards,

    gh-

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  • gchalive
    gchalive over 15 years ago
    Hi..
     
    I would want RC to retain only few logic gates in my design.
    It may map the rest of the logic optimally. I have found the attribute to set this to happen. It is, set_attribute preserve true <cell_name>
     
    Thanks for your response.
     
    Thanks
    gchalive
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