RTL Compiler does not make use of "non-conventional" multiple-output cells

Hi,

I will try to be brief, but if you need any detail please ask me,

in summary, the problem is: if I describe in my liberty file a cell with multiple-outputs, the mapper (RTL Compiler) is not able to make use of it ... (if I put them together with convetional single-output cells, the tool just use the single-output cells, if I put only the multiple-output cells, it is not able to complete the mapping because does nor recognize the fundamental basic functions needed)

probable important points:
    1) There is no syntax error during the execution
    2) The logic functions of the outputs does not share inputs, an example is S1 = !(A & B) and S2 = !(C + D), so they are not like a Full-Adder..
    3) I've been using functional liberties (.lib with no information about power or timing, just the logic functions and the area set to "1"),

If I use a liberty like this one below, which is basically a cell with two "encapsulated" inverters, the tool does not even recognize the existence of inverters in the library,

  cell(two_encapsulated_invs){
    area : 1;
    pin(a){ direction : input; }
    pin(b){ direction : input; }
    pin(Z0){   direction : output;
                  function : "!a";
                  timing(){  related_pin : "a";  }
              }
    pin(Z1){  direction : output;
                 function : "!b";
                 timing(){  related_pin : "b";  }
              }
  }

so my question is:
 - Is it possible to make RTL Compiler able to use multiple-output cells if they are not the "expected kind" like a full-adder?
   (in any version of it, ours is v08.10-s222_1 (32-bit), built Mar 25 2009 (32-bit), but the question is more like to know if the map algorithm is aware of such situation, or what command would make it aware)

thank you,
best regards