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LEF in synthesis flow

diablo

Hi,

In RTL compiler synthesis flow, i have

set_attribute interconnect_mode ple /

And, i have inlcuded the cap table as well

set_attribute cap_table_file {$CAP_TABLE/bst.cap } 

Do i need to include the LEF library for std cells and io cells as well for correct interconnect delay estimation even after including cap table?

It seems including LEF file gives significant difference in total number of cells and area after synthesis as reported from RTL compiler. Below is the snippet of area report for two flow, 

one excluding LEF

 Cells       Cell Area       Net Area

 23283       715947       391632

and the other including LEF file 

Cells       Cell Area       Net Area

 22664       967042       246572

 Which one is correct flow? Or, which one is the better flow?

Thanks for your suggestions and your time.

Regards. 

Parents

  • Thanks gh for the suggestion. I would go with recommended LEF flow.

    But I still do not understand what extra information does LEF provides that help the synthesis tools in synthesizing the logic? Could you please elaborate on the utility of LEF file in the synthesis process. I was in the impression that most of the timing,area and functionality information is already in the .lib file for all the std and io cells. So, the only extra information the synthesis tool needs is to estimate the interconnect delay. I am assuming the pin loading information from liberty file and the RC equivalent is estimated from CapTable, and that loading value is used in timing table in liberty file to pick up the right timing.

    While i was going through RC documentation, i found there is synthesize -to_placed as well. I usually do synthesize  -to_mapped only. If I was doing synthesize -to_placed then it makes more sense to read in def_file or lef_file. What kind of advantage does synthesize -to_placed provide over synthesize -to_mapped? Is synthesize -to_placed also the recommeded flow over synthesize -to_mapped before releasing the netlist to the Encounter for placement and routing.?

    Thanks for you help.

    Regards. 

     

Reply

  • Thanks gh for the suggestion. I would go with recommended LEF flow.

    But I still do not understand what extra information does LEF provides that help the synthesis tools in synthesizing the logic? Could you please elaborate on the utility of LEF file in the synthesis process. I was in the impression that most of the timing,area and functionality information is already in the .lib file for all the std and io cells. So, the only extra information the synthesis tool needs is to estimate the interconnect delay. I am assuming the pin loading information from liberty file and the RC equivalent is estimated from CapTable, and that loading value is used in timing table in liberty file to pick up the right timing.

    While i was going through RC documentation, i found there is synthesize -to_placed as well. I usually do synthesize  -to_mapped only. If I was doing synthesize -to_placed then it makes more sense to read in def_file or lef_file. What kind of advantage does synthesize -to_placed provide over synthesize -to_mapped? Is synthesize -to_placed also the recommeded flow over synthesize -to_mapped before releasing the netlist to the Encounter for placement and routing.?

    Thanks for you help.

    Regards. 

     

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