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LEF in synthesis flow

diablo

Hi,

In RTL compiler synthesis flow, i have

set_attribute interconnect_mode ple /

And, i have inlcuded the cap table as well

set_attribute cap_table_file {$CAP_TABLE/bst.cap } 

Do i need to include the LEF library for std cells and io cells as well for correct interconnect delay estimation even after including cap table?

It seems including LEF file gives significant difference in total number of cells and area after synthesis as reported from RTL compiler. Below is the snippet of area report for two flow, 

one excluding LEF

 Cells       Cell Area       Net Area

 23283       715947       391632

and the other including LEF file 

Cells       Cell Area       Net Area

 22664       967042       246572

 Which one is correct flow? Or, which one is the better flow?

Thanks for your suggestions and your time.

Regards. 

Parents
  • Hi diablo,

    There are two type of LEF information that RC can use. Tech LEF & MACRO LEF.  The tech LEF has all routing pitch, width & spacing for each metal layer. Res is also included in the tech LEF if not specified in the CapTable. Using this information RC can then index correctly into the captable to find correct side wall cap, fringe cap, and area cap. This is done using PLE interconnect mode which is more advanced and more accurate then area based wire load models. Strictly speaking no MACRO lef are required to run PLE mode. However to run synth -to_place you will need all LEF both MACRO and TECH else this will fail since synth -to_place runs EDIS under the hood. Why is running synth -to_place better then straight synth -to_map. Synth -to place will complete a placement then optimize the design based on this placement. This can then account for long wires crossing say memories or complications based on a port location. Synth -to_place also has a number helpful congestion analysis features and auto/semi-auto fixing mechanism.

    Hope this helps,

      Mike
Reply
  • Hi diablo,

    There are two type of LEF information that RC can use. Tech LEF & MACRO LEF.  The tech LEF has all routing pitch, width & spacing for each metal layer. Res is also included in the tech LEF if not specified in the CapTable. Using this information RC can then index correctly into the captable to find correct side wall cap, fringe cap, and area cap. This is done using PLE interconnect mode which is more advanced and more accurate then area based wire load models. Strictly speaking no MACRO lef are required to run PLE mode. However to run synth -to_place you will need all LEF both MACRO and TECH else this will fail since synth -to_place runs EDIS under the hood. Why is running synth -to_place better then straight synth -to_map. Synth -to place will complete a placement then optimize the design based on this placement. This can then account for long wires crossing say memories or complications based on a port location. Synth -to_place also has a number helpful congestion analysis features and auto/semi-auto fixing mechanism.

    Hope this helps,

      Mike
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