LEF in synthesis flow

Hi,

In RTL compiler synthesis flow, i have

set_attribute interconnect_mode ple /

And, i have inlcuded the cap table as well

set_attribute cap_table_file {$CAP_TABLE/bst.cap } 

Do i need to include the LEF library for std cells and io cells as well for correct interconnect delay estimation even after including cap table?

It seems including LEF file gives significant difference in total number of cells and area after synthesis as reported from RTL compiler. Below is the snippet of area report for two flow, 

one excluding LEF

 Cells       Cell Area       Net Area

 23283       715947       391632

and the other including LEF file 

Cells       Cell Area       Net Area

 22664       967042       246572

 Which one is correct flow? Or, which one is the better flow?

Thanks for your suggestions and your time.

Regards.