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rtl synthesis

vlsiproject

 what are the input files required for rtl synthesis using rtl compiler(encounter)???

  • u need to define the technology libraries that would tell the compiler about the function, timings, power, aera etc of each gate. As of now, i am using a pre defined university library.

    and yes, you would need your .v (or .sv) file as well. :)

    I am stuck with Clock Gating analysis in my RTL synthesis. I have to reduce power of my system. and theoritically i know how to do it. but whenever i am trying to use a clock gating directive, the tool wont synthesize after that. it shows me an error about "FF_Feedback " ignored. what all do i need to speciy to the consol other thatn the lp_clock_gating true directive?

    I am at a pretty basic level of RTL usage myself, but it seems DC synthsis tool is more simpler to use in this regard.

     Well, i have my project submission 2morow, so i think i wont be getting a reply anytime soon, but would still like to know this concept.

     

    manraj

  •  Hi vlsiproject,

    At a minimum

    + liberty timing libraries

    + run script

    + HDL

     but depending on what you are trying to do you could need other collateral such as

     + LEF physical libaries

    + Floorplan DEF

    + capTbl

    + Yield coefficient

    + Toggle activity file

    + worst case power libraries

    + DFT related files

    No single answer here but hopefully these helps you

     
    Gh

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