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RTL Compiler: Unavoid the tiecells from library

haikom over 14 years ago

Hi,

after I synthesized the VHDL-code using RTL Compiler 9.10, I want to insert TIE1 and TIE0 cells, but I got this error:

##################

rc:/> insert_tiehilo_cells -hi TIE1 -lo TIE0 top_cell_name

Error : Specify a tiecell which is not avoided. [UTUI-215] [insert_tiehilo_cells]
: Unavoid the tiecells from library.

##################

Can someone give me a hint, how to "Unavoid"the tiecells?

Kind regards

haikom

grasshopper over 14 years ago

Hi haikom,
set_attribute avoid false [find /libraries -libcell TIE1]
set_attribute avoid false [find /libraries -libcell TIE0]
should do the trick for you

gh-
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