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Input port associated to Clock

sureshm

Hi all,

Is there a way to get the clocks reaching the given flip-flop???

For Ex:  If i give a get register clock pin,  my_reg/CK , How do i retrieve the clock being propagated to this pin ?

get_attr [ get_pins my_reg/CK] clocks  in PT/DC.

how would really acheive this in RC ?

This is to identify the ports being clocked by the given clock name as i have minimum info about the input ports associated with each clock of the design and hence i would write a procedure to find the info, which requires above need?

Also, How to get only the clock pins of the whole designs instead of all register inputs pins ?

thanks in advance

suresh  

 

 

  •  Hi Suresh,

     I think the propagated_clock attribute is what you are looking for

    rc:/> get_attr -h *clock pin

    Usage: get_attribute <string> [<object>+]

        <string>:
            attribute name
        [<object>+]:
            object of interest (must be unique)

        attribute categories: dft opt tim

        attribute name: hold_uncertainty_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Uncertainty of ideal clock waveform edges for hold analysis.

        attribute name: lssd_master_clock
              category: opt (controls optimization)
           object type: pin
           access type: read-write
             data type: pin
         default value:
                  help: Defines the master clock port related to this slave clock port.

        attribute name: network_early_latency_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Network latency of the ideal waveform edges for early analysis.

        attribute name: network_late_latency_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Network latency of the ideal waveform edges for late-mode (setup) analysis.

        attribute name: setup_uncertainty_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Uncertainty of ideal clock waveform edges for setup analysis.

        attribute name: source_early_latency_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Source latency of the ideal waveform edges for early analysis.

        attribute name: source_late_latency_by_clock
              category: tim (controls timing optimization and returns timing information)
           object type: pin
           access type: read-write
             data type: tcl list of EnvClks and corresponding delays
         default value:
                  help: Source latency of the ideal waveform edges for late-mode (setup) analysis.

        attribute name: user_test_receiver_init_clock
              category: dft (controls design for test)
           object type: pin
           access type: read-write
             data type: string
         default value:
                  help: User specified test receiver clock to latch data from the boundary cell.

    gh-

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