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RTL Compiler: Area "what-if" anaylsis / Area Constraints

maxbaker

Hi Forums,

I'm trying to push RC to see what the best area I can get out of a synthesis run.  The design I have meets timing very very easily and so the simplest of cells are chosen (2-input logic gates).  I would like to see how small I could make this design and push the tool to choose more complex gates out of the library and reduce the gate count.    

 Another oddity: The design has a bunch of asynch preset FFs, but synthesis grabs a flop w/ both reset and preset  instead of the flop w/ preset only.   I'm guessing this is because it still meets timing handily, so it doesn't bother looking for a better one?

 I'm hoping there is an attribute I can set to quickly do "what-if" type analysis on area instead of having to create fake DEFs and pushing them through the tool.

 

tia,

-m

  •  Hi Tia,

    RC will minimize area by default. Complex gates do not always ensure minimal area.Smaller cells tend to have a richer set of drive strengths. In addition, often time, you will still need to buffer and by keeping all clustered you do not remove that need whereas smaller cells could be distributed and limit this need. 

     As per the issue of the degenerated cell, there are cases where due to some performance reason RC uses a FF with extra functionality and ties de-asserted the unused functionality but the case you describe does not sounds like that case. You can try the change_link command with one of those flops and quickly confirm whether your timing would still be met and area would be smaller. If that is the case, then I would look more closely at the log file to understand why RC picked it.

    Last but not least, I am not saying RC may not pick an area inefficicent implementation but it certainly should not, especially if the timing is easily met as you indicated

     

    hope this helps,

    gh-

     

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