Stats

  • Locked Locked
  • Replies 1
  • Subscribers 62
  • Views 15873
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Identifying Half Cycle paths in the design

sureshm

Hi all,

Although it may sound very trivial task, I would like to get all the half-cycle paths present in my  design, which may go for the review, using RTL ? Any hints in achieving this task ?

 Also,  if there is equivalent way of  getting attributes to the timing paths like we have it in pt_shell??

Thanks

suresh

  •  Hi Suresh,

     not clear with respect to which tool you are asking but CCD is probably the ideal tool for this kind of work. More importantly, can you clearly articulate what your definition of a half-cycle path is. Does it matter if it is rise to rise or rise to fall ? Does it matter what the clock names are ? Does it have to be half cycle on some clock ? How do you define the master or not halfy-cycle path ? In other words, what would an assertion defining a half-cycle path look like ? As per RTL Compiler, you can programmatically access all data in a timing path using the -format_proc option of report timing. I suggest you work with your local AE on this since it is not documented.

     

    gh-

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.