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how to uniquify the designWare in LEC

Hi everyone, when we use LEC to do check between rtl code and netlist. The DW_multi_2_stage is used in rtl code, after synthesis, the low bits of the DW output are optimized, they disappear in netlist. And this DW is treated as BlackBox in LEC, then the LEC reports the mismatch between rtl and netlist for this BB.

Does anyone have the experience or solution for this issue.

grasshopper over 14 years ago

Did u try the following solution article ?

http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11569526;searchHash=843acfe8d72306ab832a531f47a4f068

As per uniquifying in dofile output of RC you can do

set_attr wlec_uniquify true /

write_do_lec ....

hope this helps,

gh-
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croy over 14 years ago

This module should not be a bbox in LEC. Are you sure you're reading in the model correctly? Also, this module will be retimed. Are you using the flow needed for that?

Please create a Service Request through support.cadence.com so an AE from Customer Support can help you.
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