• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. Multiplier Selection in RTL compiler

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 65
  • Views 15106
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Multiplier Selection in RTL compiler

AliShami
AliShami over 14 years ago

Hello Everyone

I am developing a new type of multiplier. For that I wrote the VHDL code, and did the synthesis with and without clock contraints. Now I want to compare this architecture with other multiplier architectures. I have got two options;

1. Create the structural VHDL code for other architectures of the multipliers. This will require hand coding and knowledge of all other architectures and will need a lot of time. It will also requite thorough testing to avoid any mistake.

2. Use RTL compiler, and somehow force the tool to synthesize desired architectures and report the area, clock and power. I was wondering

a) if its possible in RTL compiler to select a specific architecture. 

b) Is there any documentation available for the kind of architectures used by RTL compiler. I just synthesized a multiplier and it got slow/booth type multiplier. This multiplier has a critical path of almost 3ns at 90nm. I always thought booth multiplier is a serial multiplier, however this one produces a result every cycle.

c) Any input on the comparison methodology that I am following will also be appreciated.

Regards

Ali

  • Cancel
  • smdunga
    smdunga over 14 years ago

    Hi Ali,

    Hope this attribute can be useful for you.

    user_speed_grade

    It can have the following values: {very_slow | slow | medium | fast | very_fast}

    Its a Read-write subdesign attribute. Allows you to choose a fixed implementation of an internal RTL Compiler component, such as a datapath component. A component can have several implementations with different speeds. RTL Compiler automatically determines which implementation to choose to meet timing and area requirements, but this attribute allows you to choose a different implementation.

    Note: If you choose to explicitly control this process through the user_speed_grade attribute, then you must do so after using the synthesize -to_generic command. Otherwise, RTL Compiler will ignore the user specified speed grade and implement an architecture that may or may not coincide with the specified speed grade.

    Rgds Srini

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • leapfrog
    leapfrog over 10 years ago
    please provide reference material for this, if available! thanks in advance !
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information