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Adding clock to CDC tool which is not a primary input but internal to design.

vaizguy

Hello,

I would like to know how do we specify internal clock pins (output of PLL internal to design) to the CONFORML tool for doing CDC checks as the 'add clock' command accepts only primary inputs as definable clocks. The design I want to perform CDC on, has clocks as inputs to the design as well as some clocks which are generated internal to the design.

Thanks, 

  • Hello This is Jack Ho from Cadence.

     

    In order to use the command "add clock" on an internal pin/net, you will need to use the "add primary input" command first, which essentially makes it a primary input. The syntax for add primary input looks like this: ADD PRimary Input < [-Net] | -Pin>> (Setup Mode)

    So your script will look something like this

    add primary input PLL/output -pin

    add clock ...

    Having said that, we have since then introduced an improved CDC solution within our CCD (Conformal Constraint Designer) product. It performs both sdc checks and CDC checks within the same tool, providing closed-loop verification of both your timing constraints and clock domain crossings. If you are going to perform clock domain checks, you would want to, first of all, validate your clock domain definitions and groupings for a more complete solution.

     

    Thanks, Jack

  • in reply to Jack Ho

    Hi, I've run into an issue where cross clock paths has not been identified by the CDC tool.  I'm working with Xilinx V5.

    The end point is a BUFGCTRL. 

    Clock Domain 1:  A differential input clock drives a IBUFDS, and outputs a single ended clock.  This clock drives a clock input on the BUFGCTRL.

    Clock Domain 2:  A control signal from a sysclk domain register, drives the control inputs of the BUGFCTRL.

    I added data association to the control signal in the sysclk domain.

    I've attempted to add a clock to the single-ended clock (output of IBUFDS) along different points along this path.  I always get a warning:  Clock <...> is not a in clock cone.

    Here is an example of the added clock:  add primary input design1/pci_clk0 -net (I've also tried -pin)

                                                                     add clock 0 design1/pci_clk0

    Do you see what I'm doing incorrectly?  Or have any other suggestions? 

    I'm stumped.

    Thank you.

    Regards,   Peter

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