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Can't time design correctly with generated clock

When the source clock for a generated clock is from an internal module, report_timing times launch and capture off of the same edge of this generated clock.

create_clock -name sclk -period 10 top/U1/U23/port2
create_generated_clock -name gclk -source sclk -divide_by 8
....

When doing timing report, the launch clock is gclk at time 0 and capture clock is gclk at time 0. So, the path always misses timing.

Have anybody seen this in their design?

Originally posted in cdnusers.org by mximdal

archive over 20 years ago

Do you mean report_timing in late mode or early mode? In early mode, launch and capture edge are both at 0.

Originally posted in cdnusers.org by synthman
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archive over 20 years ago

Another thing to check is to use 'report_clocks -generated' to see if the phase shifts for this clock are correct.

Originally posted in cdnusers.org by synthman
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archive over 20 years ago

Synthman,

Thanks for the reply. Figured out that the clock should be coming from top port. So things are fine now. ;-)

Originally posted in cdnusers.org by mximdal
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