• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. Problems in custom design verification using LEC

Stats

  • Locked Locked
  • Replies 3
  • Subscribers 62
  • Views 14080
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Problems in custom design verification using LEC

sunkimi
sunkimi over 13 years ago
Hi all,

There is a problem when using LEC10.1 check for custom design (named module A).I checked the Module A two times. First, I check it alone, that is set module A as root module, and then abstract and compare. The result shows that the Golden and Revised design is equivalent.Second, I check it during hierarchical comparison. Problems come here. The constraints are the same as the first comparison. But the result shows the logic between the Golden and Revised is not equivalent.I find that reason may be is that during hierarchical comparison the LEC cannot correctly model the abstracted circuit.

When run first comparison, LEC can find DLAT as a key point in abstracted circuit, But during the second hierarchical comparison LEC cut the combination feedback as a key point (DLAT has a combination feedback to hold the value). That confused me. How to control LEC to model the circuit.
The following message showed during the hierarchical comparison. But not appeared during the first comparison.

// (F3) Cut 21 feedback loop(s), 14 with name

I have tried some ways to fix the problem. But it cannot works.  

Any good ideas?

Thanks.

 
  • Cancel
  • archive
    archive over 13 years ago

    Hi sunkimi,

    It sounds like abstraction engine results are different on module vs design level abstraction.

    For hierarchical comparison, I would try to abstract module A first, then follow it up by rest of the abstraction. abstract logic -module A abstract logic ..rest of the design.. ..run hier compare.. See if this helps.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • sunkimi
    sunkimi over 13 years ago

    hi sean,

    Thank you for your reply.
    I have tried the way you proposed. Yes, it can work for module A. But other modules met the problem the same as module A did. That is other module (module B) has a different result from the first comparison.The state element (DLAT/DFF) cannot be abstracted the same one during module and hierarchical comparison.I do not know the reason. It’s a bad thing for me. 

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • croy
    croy over 13 years ago

    Hi sunkimi

     

    Please create a Service Request at http://support.cadence.com so someone from Customer Support can help you.

     

    Chrystian

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information