• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Logic Design
  3. custom wireload model from first encounter

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 61
  • Views 14400
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

custom wireload model from first encounter

archive
archive over 20 years ago

hi

Does anyone use this wireload model to synthesis in synopsys ?

i have huge interconnect delay after using this cwlm .

Is this normal ?

thanks


Originally posted in cdnusers.org by ccl123
  • Cancel
Parents
  • archive
    archive over 19 years ago

    Hi,

    We don't use custom wireload models. Our synth is run using the smallest "realistic" model in the library (auto selection is disabled), and is purely use to allow us to have some load on nets when running optimisation. Our real aim is to get a netlist into layout as quickly as possible, and utilise post-placement optimisation to achieve better timing results.

    The only thing we try to push for in synth is the fastest architecture for things like adders etc. However we do try to ensure that the resultant netlist doesn't utilise many high drive-strength cells (instead reserving them for the layout opt phase).

    Whether using custom or library wireloads, you run into issues when timing between blocks or at the toplevel. Yet in placement, the decisions made by the synth tool can be completely wrong.

    Of course, someone will now come along and give an alternative view.......

    CD


    Originally posted in cdnusers.org by crispy_duck
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • archive
    archive over 19 years ago

    Hi,

    We don't use custom wireload models. Our synth is run using the smallest "realistic" model in the library (auto selection is disabled), and is purely use to allow us to have some load on nets when running optimisation. Our real aim is to get a netlist into layout as quickly as possible, and utilise post-placement optimisation to achieve better timing results.

    The only thing we try to push for in synth is the fastest architecture for things like adders etc. However we do try to ensure that the resultant netlist doesn't utilise many high drive-strength cells (instead reserving them for the layout opt phase).

    Whether using custom or library wireloads, you run into issues when timing between blocks or at the toplevel. Yet in placement, the decisions made by the synth tool can be completely wrong.

    Of course, someone will now come along and give an alternative view.......

    CD


    Originally posted in cdnusers.org by crispy_duck
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information