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Properly optimizing enable to clock gating enable

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Hi,

I am curious to know how you handle the path to clock gating enable  pin.

I have a design containing multiple level of clock gating on the clock network and when synthesizing using ideal clock all my patht o enable pins have a full  cycle but when My CTS will introduced the latency of the network will reduce the available time to reach those pins.

I understand I could perform post CTS optimization but I would prefer a more robust method to constraint those in ideal clock mode.

I'am thinking of the 2 following approach and would like to hear from you if you have use them or if you have used any others.

- max_delay to enable pins equal to (clock period - expected network latency post clock gating element)
- defining generated clock after each clock gating element with different latency

Those 2 methods have the inconvenience of requiring a lot of data management  :(

Thanks for your help,
Eric.


Originally posted in cdnusers.org by evenditti
Parents
  • Firstly, I’m assuming you’ve got a latch on each gate to prevent glitches?

    Do all of your clock-gates have simple names that are unique (eg RC_CG_* like Rtl-Compiler uses)? If so, then you could “max-delay” constrain them in Rtl-Compiler by finding every gating cell’s latch “d” pin using “find” and wildcards (such that you embed the find inside the command setting the max-delay). Now use “write_sdc”. If the constraint is applied right, you’ll have one line in the synth scripts and one per gate in the sdc.

    Then you just need to pick the value for the constraint that is a compromise between over-constraining gates that easily meet timing, and only leaving a manageable number of fails to fix by hand after CTS.

    Of course the real solution is to architect the system/design/software for low-power better in the first place, but I’d run on too long if I started that one!

    Originally posted in cdnusers.org by crispy_duck
Reply
  • Firstly, I’m assuming you’ve got a latch on each gate to prevent glitches?

    Do all of your clock-gates have simple names that are unique (eg RC_CG_* like Rtl-Compiler uses)? If so, then you could “max-delay” constrain them in Rtl-Compiler by finding every gating cell’s latch “d” pin using “find” and wildcards (such that you embed the find inside the command setting the max-delay). Now use “write_sdc”. If the constraint is applied right, you’ll have one line in the synth scripts and one per gate in the sdc.

    Then you just need to pick the value for the constraint that is a compromise between over-constraining gates that easily meet timing, and only leaving a manageable number of fails to fix by hand after CTS.

    Of course the real solution is to architect the system/design/software for low-power better in the first place, but I’d run on too long if I started that one!

    Originally posted in cdnusers.org by crispy_duck
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