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Properly optimizing enable to clock gating enable

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Hi,

I am curious to know how you handle the path to clock gating enable  pin.

I have a design containing multiple level of clock gating on the clock network and when synthesizing using ideal clock all my patht o enable pins have a full  cycle but when My CTS will introduced the latency of the network will reduce the available time to reach those pins.

I understand I could perform post CTS optimization but I would prefer a more robust method to constraint those in ideal clock mode.

I'am thinking of the 2 following approach and would like to hear from you if you have use them or if you have used any others.

- max_delay to enable pins equal to (clock period - expected network latency post clock gating element)
- defining generated clock after each clock gating element with different latency

Those 2 methods have the inconvenience of requiring a lot of data management  :(

Thanks for your help,
Eric.


Originally posted in cdnusers.org by evenditti
Parents

  • Ever been beaten by that one due to the clock latency making your enable being seen one cycle too late?
     

    Hence my comment about needing to design/structure this from scratch. if the system is designed to cope with the uncertainty, then it shouldn't be a problem (BOCTAOE)

    By the way, this structuring becomes even more important when you start to consider multiple-supply voltages, because turning the power onto a block is far slower than turning a clock on, and if your s/w can’t handle this delay/prediction for clocks, you’ll never manage it for voltage!!).

    CD


    Originally posted in cdnusers.org by crispy_duck
Reply

  • Ever been beaten by that one due to the clock latency making your enable being seen one cycle too late?
     

    Hence my comment about needing to design/structure this from scratch. if the system is designed to cope with the uncertainty, then it shouldn't be a problem (BOCTAOE)

    By the way, this structuring becomes even more important when you start to consider multiple-supply voltages, because turning the power onto a block is far slower than turning a clock on, and if your s/w can’t handle this delay/prediction for clocks, you’ll never manage it for voltage!!).

    CD


    Originally posted in cdnusers.org by crispy_duck
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