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Properly optimizing enable to clock gating enable

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Hi,

I am curious to know how you handle the path to clock gating enable  pin.

I have a design containing multiple level of clock gating on the clock network and when synthesizing using ideal clock all my patht o enable pins have a full  cycle but when My CTS will introduced the latency of the network will reduce the available time to reach those pins.

I understand I could perform post CTS optimization but I would prefer a more robust method to constraint those in ideal clock mode.

I'am thinking of the 2 following approach and would like to hear from you if you have use them or if you have used any others.

- max_delay to enable pins equal to (clock period - expected network latency post clock gating element)
- defining generated clock after each clock gating element with different latency

Those 2 methods have the inconvenience of requiring a lot of data management  :(

Thanks for your help,
Eric.


Originally posted in cdnusers.org by evenditti
Parents

  • CD,

    Well I have not yet seen a chip trying to do cycle accurate power up/down but I have seen that done (and done it myself) for clock fior more than 10 years.  As you say the latency through power switches is far too great.

    However I do agree that good planing is the key to all this unfortunately it is often quite difficult to achieve down to the lower level when re-using soft IPs  coming from internal team or outside. In general we end up witha  well define chip level clock architecture to go to the various IP with limited number of clock gating. isolation cells and level shifter. Where we start havign problems is when we reach the soft IP blocks which have all been written following different guidelines (Today's guidelines are not the one used 1 or 2 years ago) and unfortunately as the management see those IPs are done there are no ressources to re-open and fix those.

    But yes good architecture is the key to a happy inplementation engineer (especially if it comes with detail clock network diagram and balancing requirement)

    How many night did I dream about this? ....


    Originally posted in cdnusers.org by evenditti
Reply

  • CD,

    Well I have not yet seen a chip trying to do cycle accurate power up/down but I have seen that done (and done it myself) for clock fior more than 10 years.  As you say the latency through power switches is far too great.

    However I do agree that good planing is the key to all this unfortunately it is often quite difficult to achieve down to the lower level when re-using soft IPs  coming from internal team or outside. In general we end up witha  well define chip level clock architecture to go to the various IP with limited number of clock gating. isolation cells and level shifter. Where we start havign problems is when we reach the soft IP blocks which have all been written following different guidelines (Today's guidelines are not the one used 1 or 2 years ago) and unfortunately as the management see those IPs are done there are no ressources to re-open and fix those.

    But yes good architecture is the key to a happy inplementation engineer (especially if it comes with detail clock network diagram and balancing requirement)

    How many night did I dream about this? ....


    Originally posted in cdnusers.org by evenditti
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