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Simulating an imported VHDL

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Hi everybody
I'm newbie in using Cadence, so pleas forgive me if my question is too banal.
I need to simulate a logic component (so far it's synthetized only in VHDL) which must control an analog circuit. To do this I've imported a VHDL file into Cadence, and it created the 3 views (entity, structural, symbol).But when I put an instance of it in the schematic I want to simulate, I receive the following error message:
Netlister: unable to descend into any of the views defined in the view list "spectre cmos_sch cmos.sch schematic veriloga ahdl" for instance ...

If I've uderstood, I must put in the view list in the Environment window another view, for simulating VHDL imprted, but I have no idea about which view I have to put in...
Thanks in advance
Paolo


Originally posted in cdnusers.org by Delfo

  • Hi Paolo,
    I suggest you to repost this in the Custom IC or Functional Verification forum this does not fall into synthesis and test area. It would be more informative to say which Cadence tool you're using.

    synthman


    Originally posted in cdnusers.org by synthman

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