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problem with reading TCF - file in RC

Alex Kli

Hi!

I have a problem with reading in TCF- data in the RC (rtl compiler).

I will shortly explain what I do:

I have a Testbench (SystemC) and a DUT (Verilog). For simulation I use "ncsc_run" and in this simulation I generate my TCF - file. This works very good so far. As a result I get a TCF - file that looks fine.

Afterwards I use the RC to synthesize my design, of coure I use a tcl - script for that.

At the end of my tcl - script I do the following:

# Annotate switching activities via TCF - file
read_tcf ../xyz.tcf

# Generate reports
report power -detail -verbose  > ./reports/map_power_tcf.txt
report power -tcf_summary > ./reports/tcf_summary.txt

The tcf_summary.txt looks like this:

-------------------------------------------------------
Total nets in design            : 4045 (100.00%)
Nets asserted                   : 69 (1.71%)
Nets computed                   : 3975 (98.27%)
Default nets                    : 0 (0.00%)
Asserted clock nets             : 0 (0.00%)
Constant nets                   : 1 (0.02%)
Net does not have TCF asserted  : 3976 (98.29%)
-------------------------------------------------------

If I understand this report right, the RC could assign toggeling - activity from the TCF - file only to 1.71% (69) of all nets!? This is very strange to me because when I look in the TCF - file, I see around 3500 entries inside concerning toggeling activity.

Even the RC tells me the following while processing:

Reading file : ../xyz.tcf
Nets/Pins asserted in TCF file : 73
Total Nets/Pins in TCF file    : 3541
-------------------------------------------------------
Asserted Primary inputs in design              : 39 (100.00%)
Total connected primary inputs in design       : 39 (100.00%)
-------------------------------------------------------
Asserted sequential outputs          : 29 (7.27%)
Total connected sequential outputs   : 399 (100.00%)
-------------------------------------------------------
Total nets in design                 : 4045 (100.00%)
Nets asserted                        : 69 (1.71%)
Clock nets                           : 0 (0.00)
Constant nets                        : 1 (0.02)
Nets with no assertions              : 3976 (98.29%)
-------------------------------------------------------
-------------------------------------------------------
Asserted Primary inputs in design              : 39 (100.00%)
Total connected primary inputs in design       : 39 (100.00%)
-------------------------------------------------------
Asserted sequential outputs          : 29 (7.27%)
Total connected sequential outputs   : 399 (100.00%)

It seems that the RC knows that there is a lot more information in my TCF - file, but because of some reason it can't assert it to the proper nets.

Maybe someone has got an idea what I do wrong?

Thanks a lot!

Alex'

Parents

  • hi!

    thanks for your fast answer!

    yes, i think too that the annotation does not line up and I think that I already found the solution for that.

    what I do is that I write out the TCF - file by simulation of the verilog RTL - file. afterwards I synthesize this RTL - file (result = netlist) and THEN I read in the TCF - file. at this point, the RC is not able anymore to map the information from the TCF - file to the current design because the net - names do not match anymore inbetween RTL - file amd NETLIST. this is why I'll try to simulte the pure netlist now and generate the TCF - file out of this simulation. then the annotations should be fine.

     Alex'

Reply

  • hi!

    thanks for your fast answer!

    yes, i think too that the annotation does not line up and I think that I already found the solution for that.

    what I do is that I write out the TCF - file by simulation of the verilog RTL - file. afterwards I synthesize this RTL - file (result = netlist) and THEN I read in the TCF - file. at this point, the RC is not able anymore to map the information from the TCF - file to the current design because the net - names do not match anymore inbetween RTL - file amd NETLIST. this is why I'll try to simulte the pure netlist now and generate the TCF - file out of this simulation. then the annotations should be fine.

     Alex'

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