starting RTL compiler and Encounter

Hi all

I am totally new to encounter. I have written a VHDL code and intended to implement it using XFAB xh035 technology. I have read some tutorials online and the manual and found out that to use RC, I have to have a source script (.tcl file) and some library files. Where can I get the .tcl file and library file? I can find some .tcl and .lib files from the XFAB design kit but they do not seem to be appropriate. I have also tried loading my vhdl file without any source script with the command read_hdl -vhdl myvhdl.vhd but nothing happened. When I load it for the second time, I will get this message:

 entity Digital_controller is
|
Warning : Replacing existing design unit. [VHDLPT-800]
        : Unit 'default:Digital_controller' in file '/home/chew/rc_digital_ctrl/VHDL/Digital_controller.vhd' on line 11, column 1.
        : A previously analyzed unit is being replaced.
Warning : Marking out-of-date unit as invalid. [VHDLPT-801]
        : Unit 'default:digital_controller-rtl' depends on overwritten unit 'default:digital_controller'.
        : A unit is considered out-of-date when a unit that it depends on is re-analyzed.
Warning : Replacing previously read Verilog module or VHDL entity. [HPT-76]
        : Replacing VHDL entity 'Digital_controller' in library 'default' with newly read VHDL entity 'Digital_controller' in the same library in file '/home/chew/rc_digital_ctrl/VHDL/Digital_controller.vhd' on line 11.
        : A newly read VHDL entity replaces any previously read Verilog module or VHDL entity in the same library if its name matches (case-insensitively) the existing module or entity.
    For instance:
        VHDL 'foo'                  replaces  VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
        VHDL 'foo' (in any library) replaces  Verilog {'FOO' or 'foo' or 'Foo' or ...} in the same library
 
A newly read Verilog module replaces any previously read Verilog module if its name matches (case-sensitively) that module.  Further, it replaces any previously read VHDL entity in the same library if its name matches (case -insensitively) that entity.
    For instance:
        Verilog 'foo' replaces    VHDL {'FOO' or 'foo' or 'Foo' or ...} in the same library
        Verilog 'foo' replaces    Verilog 'foo' only
    In addition:
        Verilog 'foo' does not replace Verilog 'FOO' and the two remain as distinct modules.

 How can I start RC? Also, for encounter, are the .lef, tlf, I/O files provided by the foundry as well?

Thank you